Semiconductor switching arrangements having a normally on and a normally off transistor are known from EP 0 063 749 B1, for example. This known switching arrangement has an n-JFET (junction field effect transistor), as a normally on component, connected in series with an n-MOSFET (metal oxide semiconductor field effect transistor), as a normally off component. The control connection of the JFET is connected to the load connection of the MOSFET, the load connection being remote from the JFET. Such a cascode circuit having a JFET and a MOSFET can be used to switch electrical loads. In this context, an actuation signal needs to be provided only for the MOSFET, since the switching state of the JFET always follows the switching state of the MOSFET on the basis of the interconnection explained above.
The dielectric strength of such a semiconductor switching arrangement is determined essentially by the dielectric strength of the JFET. The dielectric strength of the MOSFET merely needs to be high enough for the MOSFET to be able to block the actuation voltage which is required for turning off the JFET.
DE 10 2006 029 928 B1 describes a cascode circuit for an n-JFET and for an n-MOSFET in which a separate actuation circuit is provided for the JFET. The MOSFET connected in series with the JFET is used merely as a protective element which, in the event of a fault in the actuation circuit of the JFET, is intended to ensure that the JFET is safely switched off. If there is no fault in the actuation circuit, the MOSFET is permanently on. In this circuit arrangement, the gate circuit, that is to say the circuit in which a charging current flows in order to turn on the JFET and a discharge current flows in order to turn off the JFET, comprises the MOSFET. Parasitic inductances on the connecting line between the two transistors, and parasitic internal inductances in the MOSFET, can have an adverse effect on the switching operations for turning the JFET on and off and can have a particularly adverse effect on switching speed.